High-speed and Low-loss Gate Drive Circuit for Normally-off SiC-JFET

Silicon carbide (SiC) power semiconductor devices are capable of being operated at higher voltages, frequencies and temperatures than silicon (Si) power devices. For the past several years, more and more SiC power switches have become available and several novel power conversion systems have been proposed recently that utilize their superior behavior. The normally-off SiC-JFET is one of these devices, features a very low on-resistance, high-speed switching and high-temperature operation compared to many other Si switches. SiC-JFET is a unipolar device and has superior switching perfor-mance and high reliability because it has no problem concerning low electron mobility at the channel and surface gate oxide reliability like a MOSFET. To achieve the best possible performance of the nor-mally-off SiC-JFET, the gate drive circuit must be adapted for its device requirements. During switching operation, the transient gate-source voltage should be around ±15V to deliver/remove the dynamic charge for charging/discharging of the gate input capacitance. During the on-state, the necessary minimum DC current must be fed into the gate to maintain low conduction of devices. Several concepts have recently been published that meet these re-quirements, but they still show certain limitations (e.g., frequency and duty cycle limitations or the need for additional cooling of driver IC due to high gate driver losses). In this paper, a novel gate drive circuit for a nor-mally-off SiC-JFET is designed and evaluated ex-perimentally. It improves the switching performance of the JFET by means of superimposed impulse voltage on the turn-on edge of the gate driver output, and can be driven with low consumption.